Vref_DQ Vref_CA VTT decoupling in DDR3 DIMM

Hi, expertsI read the standard "DDR3 SDRAM Unbuffered DIMM Design Specification"On the page 32, it states three kinds of decoupling for VTT,Vref_DQ,Vref_CApower rail:1 VTT, Minimum of one decoupling capacitor to VDD per every two terminationresistors2 Vref_CA,Minimum of one decoupling capacitor to VDD per DRAM3 Vref_DQ,Minimum of one decoupling capacitor to VSS per DRAM.Confusion:Why VTT decoupling capacitor to VDD not VSS(usually GND)? will this increase noise coupling between VTT and VDD?Vref_CA and Vref_DQ has same function as the reference voltage for SSTL-15.Vref_CA decoupling capacitor connected to VDD, but the Vref_DQ connected to VSS.I think decoupling capacitors of all above power rails should be connected to VSS and corresponding power rail net, this will be better decoupled. Thanks.Tesla
emcesd 8 years 5 months 1 day

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Answered byemcesd 8 years 5 months 26 days
Hi, SenThanks.You provide another point of view.Tesla.At 2012-06-13 00:55:06,"Sen Velmurugan"  wrote:>Corrected/Updated version...>>On 6/11/2012 6:38 PM, Sen Velmurugan wrote:>> Statement: VTT, Minimum of one decoupling capacitor to VDD per every >> two termination resistors>>>> Question: Why VTT decoupling capacitor to VDD not VSS(usually GND)? >> will this increase noise coupling between VTT and VDD?>>>> Ans: Here the answer is hiding in the requirement "per every two >> termination resistor" , the fact is VDDQ is "decoupled" w.r. to VTT >> instead of VSS. The reason is When high side mosfet of the buffer is  >> turned ON, for logic HI, the current flow is from VDDQ to mosfet to >> Termination Resistor to VTT power supply. Signal is switched w.r.t. >> VTT,  So we need to decouple the Buffer's VDDQ pin to VTT, not to VSS.>> For logic LOW, the current flow from VTT --  Termination Resistor  --- >> low side mosfet to VSS is less inductive.>>>> Goal is to dump the noise to signalling reference right ?, there is no >> worry of noise coupling between VTT and VDDQ due this decaps.>>>> Decoupling Vref depends on how Vref is generated, decoupled usually >> w.r.t GND. There is also a idea about connecting a cap to VDD from >> Vref.  So any variation in the VDD is tracked by Vref. Here the need >> and size of cap matters and need to be ascertained during DVT.>>>> In Tesla' situation it is better to ask DRAM vendor, they know their >> internal buffers read circuit implementation.>> May be Vref w.r.t to +ve or -ve i/p of opAmp.  I feel this requirement >> is DRAM driven than a layout driven choice.>> As matter of fact, any layout recommendation from vendor data sheet >> should not be blindly followed and situation varies.>>>> As far as noise on the Vref due to dual(voltage divider) caps is a >> "past" event, in the sense the data is latched w.r.t to DQS clock and >> Vref after all SSO is complete and lot of time has elapsed(half data >> period). So only a large droop on VDDQ can be transferred to Vref with >> large cap only, a small cap won't pass the low freq event.>>>> Thanks>> Sen>
Answered byzhenwwan 8 years 5 months 27 days
My opinion: there should be a very low impedence between the power plane and gnd plane in a good design. Two plane adjacent in core board, adequate decoupling capacitors(low esr and low body inductance), integrite return path... will be the same thing. So the noise on power plane will return back to gnd plane. So power plane is the same as gnd plane in AC.BRZhenwei(Jason) WangCisco Systems (Shanghai) Video Technology Co., Ltd.-----
Answered bysen.velmurugan 8 years 5 months 27 days
Corrected/Updated version...On 6/11/2012 6:38 PM, Sen Velmurugan wrote:> Statement: VTT, Minimum of one decoupling capacitor to VDD per every > two termination resistors>> Question: Why VTT decoupling capacitor to VDD not VSS(usually GND)? > will this increase noise coupling between VTT and VDD?>> Ans: Here the answer is hiding in the requirement "per every two > termination resistor" , the fact is VDDQ is "decoupled" w.r. to VTT > instead of VSS. The reason is When high side mosfet of the buffer is  > turned ON, for logic HI, the current flow is from VDDQ to mosfet to > Termination Resistor to VTT power supply. Signal is switched w.r.t. > VTT,  So we need to decouple the Buffer's VDDQ pin to VTT, not to VSS.> For logic LOW, the current flow from VTT --  Termination Resistor  --- > low side mosfet to VSS is less inductive.>> Goal is to dump the noise to signalling reference right ?, there is no > worry of noise coupling between VTT and VDDQ due this decaps.>> Decoupling Vref depends on how Vref is generated, decoupled usually > w.r.t GND. There is also a idea about connecting a cap to VDD from > Vref.  So any variation in the VDD is tracked by Vref. Here the need > and size of cap matters and need to be ascertained during DVT.>> In Tesla' situation it is better to ask DRAM vendor, they know their > internal buffers read circuit implementation.> May be Vref w.r.t to +ve or -ve i/p of opAmp.  I feel this requirement > is DRAM driven than a layout driven choice.> As matter of fact, any layout recommendation from vendor data sheet > should not be blindly followed and situation varies.>> As far as noise on the Vref due to dual(voltage divider) caps is a > "past" event, in the sense the data is latched w.r.t to DQS clock and > Vref after all SSO is complete and lot of time has elapsed(half data > period). So only a large droop on VDDQ can be transferred to Vref with > large cap only, a small cap won't pass the low freq event.>> Thanks> Sen
Answered byweirsi 8 years 5 months 27 days
Zhenwei, the problem is how much is enough? By judicious planning of theboard stack-up and routing, a design will tolerate much higher cavityimpedance without either EMC or signaling issues. Mixed referencesshould be used when the design and production costs they incrementallyimpose are outweighed by cost saved used using less material.SteveOn 6/11/2012 6:58 PM, Zhenwei Wang (zhenwwan) wrote:> My opinion: there should be a very low impedence between the power plane and > gnd plane in a good design. Two plane adjacent in core board, adequate > decoupling capacitors(low esr and low body inductance), integrite return > path... will be the same thing. So the noise on power plane will return back > to gnd plane. So power plane is the same as gnd plane in AC.>> BR> Zhenwei(Jason) Wang> Cisco Systems (Shanghai) Video Technology Co., Ltd.>> -----
Answered bysen.velmurugan 8 years 5 months 27 days
Statement: VTT, Minimum of one decoupling capacitor to VDD per every two termination resistorsQuestion: Why VTT decoupling capacitor to VDD not VSS(usually GND)? will this increase noise coupling between VTT and VDD?Ans: Here the answer is hiding in the requirement "per every two termination resistor" , the fact is VDDQ is "decoupled" w.r. to VTT instead of VSS. The reason is When high side mosfet of the buffer is  turned ON, for logic HI, the current flow is from VDDQ to mosfet to Termination Resistor to VTT power supply. Signal is switched w.r.t. VTT,  So we need to decouple the Buffer's VDDQ pin to VTT, not to VDD.No need for the decap btw Buffer's VSS to VTT , because VSS is much more robust than VDDQ to supply necessary instantaneous current for logic LOW.Goal is to dump the noise to reference right, there is no worry of noise coupling between VTT and VDDQDecoupling Vref depends on how Vref is generated, decoupled usually w.r.t GND. There is also a idea about connecting a cap to VDD from Vref.  So any variation in the VDD is tracked by Vref. Here the need and size of cap matters and need to be ascertained during DVT.In Tesla' situation it is better to ask DRAM vendor, they know their internal buffers read circuit implementation.May be Vref w.r.t to +ve or -ve i/p of opAmp.  I feel this requirement is DRAM driven than a layout driven choice.As matter of fact, any layout recommendation from vendor data sheet should not be blindly followed and situation varies.As far as noise on the Vref due to dual caps is a "past" event, in the sense the data is latched w.r.t to DQS clock and Vref after all SSO is complete and lot of time has elapsed(half data period). So only a large droop on VDDQ can be transferred to Vref with large cap only, a small cap won't pass the low freq event.ThanksSen
Answered byemcesd 8 years 5 months 28 days
Hi, SteveYour summary is more clear than mine.My board is FPGA based system using both DIMM and memory chip, so your second and fourth guideline is suitable for me.Thanks a lot.Best Regards.Tesla. At 2012-06-11 13:07:05,"steve weir"  wrote:Tesla, I believe the various considerations have been detailed earlier in the thread, but a quick summary:We want to maximize S/N at the receiver.  That means we want to pay attention to how the signal launches and what path it takes to the receiver. If:  The transmission path uses Vddq as the reflection plane as recommended from end to end, then couple Vtt to Vddq.If:  The transmission path uses Vss as the reflection plane from end to end, then couple Vtt to Vss.If:  The transmission path uses mixed references as in an offset stripline then couple to both Vddq and Vss.If:  The transmission line uses multiple references as in the signal references Vddq over part of the path and Vss over another, then you will need to bypass the cavities heavily.Steve.On 6/10/2012 6:49 PM, Tesla wrote:Hi, SteveVtt is nominally 0.5 * Vdd, but i think vtt is usually is generated by a chip. because it will sink or source current.Thanks.TeslaAt 2012-06-08 15:11:22,"steve weir"  wrote:>Vtt is nominally 0.5 * Vdd.  In a simple topology where Vtt is derived >with a resistor divider, two caps of equal value one to each rail would >maintain Vtt at 0.5Vdd across frequency.>>Steve>On 6/7/2012 11:29 PM, Tesla wrote:>> Hi, experts>> I read the standard "DDR3 SDRAM Unbuffered DIMM Design Specification">> On the page 32, it states three kinds of decoupling for >> VTT,Vref_DQ,Vref_CApower rail:>> 1 VTT, Minimum of one decoupling capacitor to VDD per every two termination>> resistors>> 2 Vref_CA,Minimum of one decoupling capacitor to VDD per DRAM>> 3 Vref_DQ,Minimum of one decoupling capacitor to VSS per DRAM.>>>> Confusion:>> Why VTT decoupling capacitor to VDD not VSS(usually GND)? will this increase >> noise coupling between VTT and VDD?>> Vref_CA and Vref_DQ has same function as the reference voltage for SSTL-15.>> Vref_CA decoupling capacitor connected to VDD, but the Vref_DQ connected to >> VSS.>>>> I think decoupling capacitors of all above power rails should be connected >> to VSS and corresponding power rail net, this will be better decoupled.>>>>   Thanks.>>>> Tesla>> 
Answered byemcesd 8 years 5 months 28 days
Hi, ExpertsThanks for your reply.In summary, I conclude Vtt decoupling method as follow:1 Use memory Chip on the board,If the traces have their return current on Vss, decouple to Vss.  If traces have their return current on Vdd, then decouple to Vdd. 2 Use DIMM on the board, the VTT decoupling is not important now. the decoupling is done on the DIMM. But there is a reference transition issue for CTL,CA,CMD line,be sure to provide enough decoupling to handle reference issue.please correct me if i miss anything.Thanks.Tesla.At 2012-06-09 01:36:38,"Smith, Larry"  wrote:>The main reason to decouple VTT is to provide a path for trace return current. > >>If the traces have their return current on Vss, then it important to decouple >to Vss.  If traces have their return current on Vdd, then decouple to Vdd.  >And if return current is on a combination of both Vdd and Vss, decouple VTT to >both of them.  >>Regards,>Larry Smith>>-----
Answered byemcesd 8 years 5 months 28 days
Hi, SteveVtt is nominally 0.5 * Vdd, but i think vtt is usually is generated by a chip. because it will sink or source current.Thanks.TeslaAt 2012-06-08 15:11:22,"steve weir"  wrote:>Vtt is nominally 0.5 * Vdd.  In a simple topology where Vtt is derived >with a resistor divider, two caps of equal value one to each rail would >maintain Vtt at 0.5Vdd across frequency.>>Steve>On 6/7/2012 11:29 PM, Tesla wrote:>> Hi, experts>> I read the standard "DDR3 SDRAM Unbuffered DIMM Design Specification">> On the page 32, it states three kinds of decoupling for >> VTT,Vref_DQ,Vref_CApower rail:>> 1 VTT, Minimum of one decoupling capacitor to VDD per every two termination>> resistors>> 2 Vref_CA,Minimum of one decoupling capacitor to VDD per DRAM>> 3 Vref_DQ,Minimum of one decoupling capacitor to VSS per DRAM.>>>> Confusion:>> Why VTT decoupling capacitor to VDD not VSS(usually GND)? will this increase >> noise coupling between VTT and VDD?>> Vref_CA and Vref_DQ has same function as the reference voltage for SSTL-15.>> Vref_CA decoupling capacitor connected to VDD, but the Vref_DQ connected to >> VSS.>>>> I think decoupling capacitors of all above power rails should be connected >> to VSS and corresponding power rail net, this will be better decoupled.>>>>   Thanks.>>>> Tesla>> 
Answered byweirsi 8 years 5 months 28 days
Tesla, I believe the various considerations have been detailed earlier in the thread, but a quick summary:We want to maximize S/N at the receiver. That means we want to pay attention to how the signal launches and what path it takes to the receiver.If: The transmission path uses Vddq as the reflection plane as recommended from end to end, then couple Vtt to Vddq.If: The transmission path uses Vss as the reflection plane from end to end, then couple Vtt to Vss.If: The transmission path uses mixed references as in an offset stripline then couple to both Vddq and Vss.If: The transmission line uses multiple references as in the signal references Vddq over part of the path and Vss over another, then you will need to bypass the cavities heavily.Steve.On 6/10/2012 6:49 PM, Tesla wrote:> Hi, Steve>> Vtt is nominally 0.5 * Vdd, but i think vtt is usually is generated by > a chip. because it will sink or source current.> Thanks.> Tesla>> At 2012-06-08 15:11:22,"steve weir"  wrote:> >Vtt is nominally 0.5 * Vdd.  In a simple topology where Vtt is derived> >with a resistor divider, two caps of equal value one to each rail would> >maintain Vtt at 0.5Vdd across frequency.> >> >Steve> >On 6/7/2012 11:29 PM, Tesla wrote:> >>  Hi, experts> >>  I read the standard "DDR3 SDRAM Unbuffered DIMM Design Specification"> >>  On the page 32, it states three kinds of decoupling for > >> VTT,Vref_DQ,Vref_CApower rail:> >>  1 VTT, Minimum of one decoupling capacitor to VDD per every two > >> termination> >>  resistors> >>  2 Vref_CA,Minimum of one decoupling capacitor to VDD per DRAM> >>  3 Vref_DQ,Minimum of one decoupling capacitor to VSS per DRAM.> >>> >>  Confusion:> >>  Why VTT decoupling capacitor to VDD not VSS(usually GND)? will this > >> increase noise coupling between VTT and VDD?> >>  Vref_CA and Vref_DQ has same function as the reference voltage for > >> SSTL-15.> >>  Vref_CA decoupling capacitor connected to VDD, but the Vref_DQ connected > >> to VSS.> >>> >>  I think decoupling capacitors of all above power rails should be > >> connected to VSS and corresponding power rail net, this will be better > >> decoupled.> >>> >>    Thanks.> >>> >>  Tesla> >>  
Answered bybuenos 8 years 5 months 28 days
Hi Tesla,VTT is generated by a chip that follows (with some delay) the voltage on a resistive voltage divider which is between VDD and GND.So, basically VTT follows VDD/2 in AC and DC, except if the divider is decoupled to GND (then DC only).Regards,Istvan Nagy-----
Answered byhermann.ruckerbauer 8 years 5 months
Hello Vinu,sorry, than I misunderstood your comment. I thought this would be thesituation you have been talking about.If you have a voltage rail collapse (so a peak on VSS and a dip on VDD)one would like to have a stable Vref.in case just a single rail would have a dip one would only want to havehalf the dip in Vref in order to stay at the midlevel.So for all of this cases the decoupling to VSS and VDD would be theright thing.But let's now take a closer look to the effects that should becompensated (based on Vref_CA):First would be a supply noise at the Controller caused by SSO. Letsassume this causes a dip in VDD. This dip will be seen directly on an CAsignal that is driving a 1 (or just switching from 0 to 1). IdeallyVref_CA would track this dip in order to allow the input receiver on theDRAM to evaluate the signal level without this noise event.Problem is, that this would require a source synchronous VREF. As thenoise will be transmitted differently on the Signal trace vs. the supplyplanes it is nearly impossible to track such an event with Vref at theDRAM. This was one of the reasons why a source sync Vref scheme was notconsidered during specification.Second thing is a supply noise on the Reference Plane. For CA thereference plane on the DIMM is VDD. So if you have noise on VDD this cancouple directly into the CA lines. in case the decoupling of Vref is toVDD then the same noise will be on the CA line as well as on the Vref inorder to compensate this noise. This is what the specification is doingwith the configuration to decouple Vref_CA to VDD. This would work finefor a system where the CA is completely and only referenced to VDD. Butin reality I have seen many system that have still mixed referencing andfor this systems a decoupling to both would be the right solution.Third effect is a voltage noise at the DRAM. This can be caused e. g.due to a read from the DRAM while it should receive commands on the CAbus. Even with a separated VDD/VDDQ on die/package this is usually asingle plane on the DIMM. So it is possible that (due to a read) the VSSgets a peak and VDD gets a dip. If Vref_CA is decoupled against VDD onlyit will follow the VDD DIP. Nevertheless the Receiver is supplied by VDDand VSS. In order to keep Vref in the center between VDD and VSS itwould require a decoupling between VDD and VSS. I think this is not asimportant as the second point, but still something that should beconsidered.Why it is not so important:The real target for Vref_CA level is not really the center between VDDand VSS but the center between high and low level of the CA signal.Driver calibration tries to make the resulting center level the same,and it would be much more difficult to define the center between highand low level. Maybe we see this compensated in future generations bysome kind of Vref training (so some voltage training similar to thetiming training (write leveling or read calibration) as we have it today.Conclusion for me: Follow the guidline with decoupling to VDD forVref_CA as long as your referencing of the CA bus is really done vs.VDD. If you have some violation of this rule this needs to be consideredin the decoupling scheme as well.I know this is difficult to describe in words. I have a section of thisin my memory training (but only in the complete version, because usually(digital) designers are not going into that level of detail). But withsome pictures the effects can be described much better.Best RegardsHermannOur next Events:================"Open the Black Box of Memory"Seminar on 09/10. October 2012Check our website or contact us for detailsEKH - EyeKnowHowHermann Ruckerbauerwww.EyeKnowHow.deHermann.Ruckerbauer@xxxxxxxxxxxxxVeilchenstrasse 194554 MoosTel.:   +49 (0)9938 / 902 083Mobile: +49 (0)176  / 787 787 77Fax:    +49 (0)3212 / 121 9008schrieb Vinu Arumugham:> Yes, but symmetric noise on VDD/VSS w.r.t some external reference> means VDD noise w.r.t VSS is 0. We never see that on practical systems!>> Thanks,> Vinu>> On 06/08/2012 01:30 PM, Hermann Ruckerbauer wrote:>> If you have a symmetric noise on VDD and VSS and a decoupling to both>> then VTT will see the same noise and everything is fine, right ?>>>> Hermann>>>>>> Our next Events:>> ================>>>> "Open the Black Box of Memory">> Seminar on 09/10. October 2012>>>> Check our website or contact us for details>>>> EKH - EyeKnowHow>> Hermann Ruckerbauer>> www.EyeKnowHow.de>> Hermann.Ruckerbauer@xxxxxxxxxxxxx>> Veilchenstrasse 1>> 94554 Moos>> Tel.:    +49 (0)9938 / 902 083>> Mobile:    +49 (0)176  / 787 787 77>> Fax:    +49 (0)3212 / 121 9008>>>>>> schrieb Vinu Arumugham:>>> Hermann,>>>>>> Regardless of whether VSS/VDD have any noise with respect to some>>> external reference, we can be sure that VDD will have noise w.r.t VSS>>> ( or if you prefer, VSS will have noise w.r.t VDD).>>> Decoupling to both rails will therefore inject noise into VTT even>>> when VDD and VSS are perfectly symmetric.>>>>>> Thanks,>>> Vinu>>>>>> On 06/08/2012 11:55 AM, Hermann Ruckerbauer wrote:>>>> Hello Vinu,>>>>>>>> not exactly, only as long as you think about VSS as fixed>>>> potential. As>>>> I mentioned I think both are equal designed ... so you can get>>>> noise on>>>> both VDD or VSS. And both will be transferred equally to VTT ...>>>>>>>> But as I mentioned .. I think this is more a question of design>>>> philosophy ...>>>>>>>> Hermann>>>>>>>> Our next Events:>>>> ================>>>>>>>> "Open the Black Box of Memory">>>> Seminar on 09/10. October 2012>>>>>>>> Check our website or contact us for details>>>>>>>> EKH - EyeKnowHow>>>> Hermann Ruckerbauer>>>> www.EyeKnowHow.de>>>> Hermann.Ruckerbauer@xxxxxxxxxxxxx>>>> Veilchenstrasse 1>>>> 94554 Moos>>>> Tel.:    +49 (0)9938 / 902 083>>>> Mobile:    +49 (0)176  / 787 787 77>>>> Fax:    +49 (0)3212 / 121 9008>>>>>>>>>>>> schrieb Vinu Arumugham:>>>>> Hermann,>>>>>>>>>>>>>>> "Nevertheless I prefer to do a decoupling to both VDD and VSS.">>>>>>>>>> If you decouple VTT to both VDD and VSS, you create a AC voltage>>>>> divider between VDD/VSS and connect it to VTT. So any noise on VDD>>>>> w.r.t VSS will be divided in half and be injected on to VTT.>>>>> Decoupling to VSS or VDD alone would avoid this noise injection. Do>>>>> you agree?>>>>>>>>>> Thanks,>>>>> Vinu>>>>>>>>>>>>>>>>>>>> On 06/08/2012 10:14 AM, Hermann Ruckerbauer wrote:>>>>>> Hello,>>>>>>>>>>>> yes, Vinu's explanation is very good!>>>>>> Just one comment: VTT is just between VDD and GND, so this would>>>>>> be no>>>>>> reason to decouple to VDD. The real issue is the referencing on the>>>>>> DIMM>>>>>> (which comes from the limited number of supply pins on the DIMM>>>>>> connector)>>>>>>>>>>>> Nevertheless I prefer to do a decoupling to both VDD and VSS.>>>>>> This is also some kind of philosophy. Some people think that VSS>>>>>> is a>>>>>> stable potential, while VDD is something unstable .. I think both>>>>>> should>>>>>> be handled with the same care. But this means, that both might have>>>>>> noise (seen in reference to some imaginary solid and fixed>>>>>> potential).>>>>>> Based on this "philosophy" i prefer to have e. g. two same size>>>>>> capacitors to VDD and GND compared to two different sized>>>>>> capacitors to>>>>>> GND (or VDD for CA).>>>>>>>>>>>> But thats just my way of looking into any "stable" potential ...>>>>>>>>>>>> Hermann>>>>>>>>>>>> Our next Events:>>>>>> ================>>>>>>>>>>>> "Open the Black Box of Memory">>>>>> Seminar on 09/10. October 2012>>>>>>>>>>>> Check our website or contact us for details>>>>>>>>>>>> EKH - EyeKnowHow>>>>>> Hermann Ruckerbauer>>>>>> www.EyeKnowHow.de>>>>>> Hermann.Ruckerbauer@xxxxxxxxxxxxx>>>>>> Veilchenstrasse 1>>>>>> 94554 Moos>>>>>> Tel.:    +49 (0)9938 / 902 083>>>>>> Mobile:    +49 (0)176  / 787 787 77>>>>>> Fax:    +49 (0)3212 / 121 9008>>>>>>>>>>>>>>>>>> schrieb Vinu Arumugham:>>>>>>> My understanding is that on the DIMM, DQ routing is referenced to>>>>>>> a VSS>>>>>>> plane and CA routing is referenced to a VDD plane. Therefore>>>>>>> VrefCA is>>>>>>> bypassed to VDD and VrefDQ is bypassed to VSS. Since VTT is used to>>>>>>> terminate CA, it is also bypassed to VDD.>>>>>>>>>>>>>> Thanks,>>>>>>> Vinu>>>>>>>>>>>>>> On 06/07/2012 11:29 PM, Tesla wrote:>>>>>>>> Hi, experts>>>>>>>> I read the standard "DDR3 SDRAM Unbuffered DIMM Design>>>>>>>> Specification">>>>>>>> On the page 32, it states three kinds of decoupling for>>>>>>>> VTT,Vref_DQ,Vref_CApower rail:>>>>>>>> 1 VTT, Minimum of one decoupling capacitor to VDD per every two>>>>>>>> termination>>>>>>>> resistors>>>>>>>> 2 Vref_CA,Minimum of one decoupling capacitor to VDD per DRAM>>>>>>>> 3 Vref_DQ,Minimum of one decoupling capacitor to VSS per DRAM.>>>>>>>>>>>>>>>> Confusion:>>>>>>>> Why VTT decoupling capacitor to VDD not VSS(usually GND)? will>>>>>>>> this increase noise coupling between VTT and VDD?>>>>>>>> Vref_CA and Vref_DQ has same function as the reference voltage>>>>>>>> for SSTL-15.>>>>>>>> Vref_CA decoupling capacitor connected to VDD, but the Vref_DQ>>>>>>>> connected to VSS.>>>>>>>>>>>>>>>> I think decoupling capacitors of all above power rails should be>>>>>>>> connected to VSS and corresponding power rail net, this will be>>>>>>>> better decoupled.>>>>>>>>>>>>>>>>      Thanks.>>>>>>>>>>>>>>>> Tesla>>>>>>>> 
Answered byhermann.ruckerbauer 8 years 5 months
If you have a symmetric noise on VDD and VSS and a decoupling to boththen VTT will see the same noise and everything is fine, right ?HermannOur next Events:================"Open the Black Box of Memory"Seminar on 09/10. October 2012Check our website or contact us for detailsEKH - EyeKnowHowHermann Ruckerbauerwww.EyeKnowHow.deHermann.Ruckerbauer@xxxxxxxxxxxxxVeilchenstrasse 194554 MoosTel.:   +49 (0)9938 / 902 083Mobile: +49 (0)176  / 787 787 77Fax:    +49 (0)3212 / 121 9008schrieb Vinu Arumugham:> Hermann,>> Regardless of whether VSS/VDD have any noise with respect to some> external reference, we can be sure that VDD will have noise w.r.t VSS> ( or if you prefer, VSS will have noise w.r.t VDD).> Decoupling to both rails will therefore inject noise into VTT even> when VDD and VSS are perfectly symmetric.>> Thanks,> Vinu>> On 06/08/2012 11:55 AM, Hermann Ruckerbauer wrote:>> Hello Vinu,>>>> not exactly, only as long as you think about VSS as fixed potential. As>> I mentioned I think both are equal designed ... so you can get noise on>> both VDD or VSS. And both will be transferred equally to VTT ...>>>> But as I mentioned .. I think this is more a question of design>> philosophy ...>>>> Hermann>>>> Our next Events:>> ================>>>> "Open the Black Box of Memory">> Seminar on 09/10. October 2012>>>> Check our website or contact us for details>>>> EKH - EyeKnowHow>> Hermann Ruckerbauer>> www.EyeKnowHow.de>> Hermann.Ruckerbauer@xxxxxxxxxxxxx>> Veilchenstrasse 1>> 94554 Moos>> Tel.:    +49 (0)9938 / 902 083>> Mobile:    +49 (0)176  / 787 787 77>> Fax:    +49 (0)3212 / 121 9008>>>>>> schrieb Vinu Arumugham:>>> Hermann,>>>>>>>>> "Nevertheless I prefer to do a decoupling to both VDD and VSS.">>>>>> If you decouple VTT to both VDD and VSS, you create a AC voltage>>> divider between VDD/VSS and connect it to VTT. So any noise on VDD>>> w.r.t VSS will be divided in half and be injected on to VTT.>>> Decoupling to VSS or VDD alone would avoid this noise injection. Do>>> you agree?>>>>>> Thanks,>>> Vinu>>>>>>>>>>>> On 06/08/2012 10:14 AM, Hermann Ruckerbauer wrote:>>>> Hello,>>>>>>>> yes, Vinu's explanation is very good!>>>> Just one comment: VTT is just between VDD and GND, so this would be no>>>> reason to decouple to VDD. The real issue is the referencing on the>>>> DIMM>>>> (which comes from the limited number of supply pins on the DIMM>>>> connector)>>>>>>>> Nevertheless I prefer to do a decoupling to both VDD and VSS.>>>> This is also some kind of philosophy. Some people think that VSS is a>>>> stable potential, while VDD is something unstable .. I think both>>>> should>>>> be handled with the same care. But this means, that both might have>>>> noise (seen in reference to some imaginary solid and fixed potential).>>>> Based on this "philosophy" i prefer to have e. g. two same size>>>> capacitors to VDD and GND compared to two different sized>>>> capacitors to>>>> GND (or VDD for CA).>>>>>>>> But thats just my way of looking into any "stable" potential ...>>>>>>>> Hermann>>>>>>>> Our next Events:>>>> ================>>>>>>>> "Open the Black Box of Memory">>>> Seminar on 09/10. October 2012>>>>>>>> Check our website or contact us for details>>>>>>>> EKH - EyeKnowHow>>>> Hermann Ruckerbauer>>>> www.EyeKnowHow.de>>>> Hermann.Ruckerbauer@xxxxxxxxxxxxx>>>> Veilchenstrasse 1>>>> 94554 Moos>>>> Tel.:    +49 (0)9938 / 902 083>>>> Mobile:    +49 (0)176  / 787 787 77>>>> Fax:    +49 (0)3212 / 121 9008>>>>>>>>>>>> schrieb Vinu Arumugham:>>>>> My understanding is that on the DIMM, DQ routing is referenced to>>>>> a VSS>>>>> plane and CA routing is referenced to a VDD plane. Therefore>>>>> VrefCA is>>>>> bypassed to VDD and VrefDQ is bypassed to VSS. Since VTT is used to>>>>> terminate CA, it is also bypassed to VDD.>>>>>>>>>> Thanks,>>>>> Vinu>>>>>>>>>> On 06/07/2012 11:29 PM, Tesla wrote:>>>>>> Hi, experts>>>>>> I read the standard "DDR3 SDRAM Unbuffered DIMM Design>>>>>> Specification">>>>>> On the page 32, it states three kinds of decoupling for>>>>>> VTT,Vref_DQ,Vref_CApower rail:>>>>>> 1 VTT, Minimum of one decoupling capacitor to VDD per every two>>>>>> termination>>>>>> resistors>>>>>> 2 Vref_CA,Minimum of one decoupling capacitor to VDD per DRAM>>>>>> 3 Vref_DQ,Minimum of one decoupling capacitor to VSS per DRAM.>>>>>>>>>>>> Confusion:>>>>>> Why VTT decoupling capacitor to VDD not VSS(usually GND)? will>>>>>> this increase noise coupling between VTT and VDD?>>>>>> Vref_CA and Vref_DQ has same function as the reference voltage>>>>>> for SSTL-15.>>>>>> Vref_CA decoupling capacitor connected to VDD, but the Vref_DQ>>>>>> connected to VSS.>>>>>>>>>>>> I think decoupling capacitors of all above power rails should be>>>>>> connected to VSS and corresponding power rail net, this will be>>>>>> better decoupled.>>>>>>>>>>>>     Thanks.>>>>>>>>>>>> Tesla>>>>>> 
Answered byhermann.ruckerbauer 8 years 5 months
Hello Vinu,not exactly, only as long as you think about VSS as fixed potential. AsI mentioned I think both are equal designed ... so you can get noise onboth VDD or VSS. And both will be transferred equally to VTT ...But as I mentioned .. I think this is more a question of designphilosophy ...HermannOur next Events:================"Open the Black Box of Memory"Seminar on 09/10. October 2012Check our website or contact us for detailsEKH - EyeKnowHowHermann Ruckerbauerwww.EyeKnowHow.deHermann.Ruckerbauer@xxxxxxxxxxxxxVeilchenstrasse 194554 MoosTel.:   +49 (0)9938 / 902 083Mobile: +49 (0)176  / 787 787 77Fax:    +49 (0)3212 / 121 9008schrieb Vinu Arumugham:> Hermann,>>> "Nevertheless I prefer to do a decoupling to both VDD and VSS.">> If you decouple VTT to both VDD and VSS, you create a AC voltage divider > between VDD/VSS and connect it to VTT. So any noise on VDD w.r.t VSS will be > divided in half and be injected on to VTT. Decoupling to VSS or VDD alone > would avoid this noise injection. Do you agree?>> Thanks,> Vinu>>>> On 06/08/2012 10:14 AM, Hermann Ruckerbauer wrote:>> Hello,>>>> yes, Vinu's explanation is very good!>> Just one comment: VTT is just between VDD and GND, so this would be no>> reason to decouple to VDD. The real issue is the referencing on the DIMM>> (which comes from the limited number of supply pins on the DIMM connector)>>>> Nevertheless I prefer to do a decoupling to both VDD and VSS.>> This is also some kind of philosophy. Some people think that VSS is a>> stable potential, while VDD is something unstable .. I think both should>> be handled with the same care. But this means, that both might have>> noise (seen in reference to some imaginary solid and fixed potential).>> Based on this "philosophy" i prefer to have e. g. two same size>> capacitors to VDD and GND compared to two different sized capacitors to>> GND (or VDD for CA).>>>> But thats just my way of looking into any "stable" potential ...>>>> Hermann>>>> Our next Events:>> ================>>>> "Open the Black Box of Memory">> Seminar on 09/10. October 2012>>>> Check our website or contact us for details>>>> EKH - EyeKnowHow>> Hermann Ruckerbauer>> www.EyeKnowHow.de>> Hermann.Ruckerbauer@xxxxxxxxxxxxx>> Veilchenstrasse 1>> 94554 Moos>> Tel.:        +49 (0)9938 / 902 083>> Mobile:      +49 (0)176  / 787 787 77>> Fax: +49 (0)3212 / 121 9008>>>>>> schrieb Vinu Arumugham:>>> My understanding is that on the DIMM, DQ routing is referenced to a VSS>>> plane and CA routing is referenced to a VDD plane. Therefore VrefCA is>>> bypassed to VDD and VrefDQ is bypassed to VSS. Since VTT is used to>>> terminate CA, it is also bypassed to VDD.>>>>>> Thanks,>>> Vinu>>>>>> On 06/07/2012 11:29 PM, Tesla wrote:>>>> Hi, experts>>>> I read the standard "DDR3 SDRAM Unbuffered DIMM Design Specification">>>> On the page 32, it states three kinds of decoupling for >>>> VTT,Vref_DQ,Vref_CApower rail:>>>> 1 VTT, Minimum of one decoupling capacitor to VDD per every two termination>>>> resistors>>>> 2 Vref_CA,Minimum of one decoupling capacitor to VDD per DRAM>>>> 3 Vref_DQ,Minimum of one decoupling capacitor to VSS per DRAM.>>>>>>>> Confusion:>>>> Why VTT decoupling capacitor to VDD not VSS(usually GND)? will this >>>> increase noise coupling between VTT and VDD?>>>> Vref_CA and Vref_DQ has same function as the reference voltage for SSTL-15.>>>> Vref_CA decoupling capacitor connected to VDD, but the Vref_DQ connected >>>> to VSS.>>>>>>>> I think decoupling capacitors of all above power rails should be connected >>>> to VSS and corresponding power rail net, this will be better decoupled.>>>>>>>>    Thanks.>>>>>>>> Tesla>>>> 
Answered byweirsi 8 years 5 months
If you want to track as closely to VCC/2 as possible then decouple to both.  If you want to track one or the other:  Vdd or Vss 1:1 then couple just to that line.SteveOn 6/8/2012 8:07 AM, Rick Collins wrote:> Can you explain why using decoupling to both ground and power would> be better than just decoupling to ground?  Aren't the power and> ground already adequately decoupled across the spectrum?  So if you> provide a low impedance to ground aren't you also providing a low> impedance to the power rail?>> Rick>>> At 03:11 AM 6/8/2012, you wrote:>> Vtt is nominally 0.5 * Vdd.  In a simple topology where Vtt is derived>> with a resistor divider, two caps of equal value one to each rail would>> maintain Vtt at 0.5Vdd across frequency.>>>> Steve>> On 6/7/2012 11:29 PM, Tesla wrote:>>> Hi, experts>>> I read the standard "DDR3 SDRAM Unbuffered DIMM Design Specification">>> On the page 32, it states three kinds of decoupling for>> VTT,Vref_DQ,Vref_CApower rail:>>> 1 VTT, Minimum of one decoupling capacitor to VDD per every two termination>>> resistors>>> 2 Vref_CA,Minimum of one decoupling capacitor to VDD per DRAM>>> 3 Vref_DQ,Minimum of one decoupling capacitor to VSS per DRAM.>>>>>> Confusion:>>> Why VTT decoupling capacitor to VDD not VSS(usually GND)? will>> this increase noise coupling between VTT and VDD?>>> Vref_CA and Vref_DQ has same function as the reference voltage for SSTL-15.>>> Vref_CA decoupling capacitor connected to VDD, but the Vref_DQ>> connected to VSS.>>> I think decoupling capacitors of all above power rails should be>> connected to VSS and corresponding power rail net, this will be>> better decoupled.>>>    Thanks.>>>>>> Tesla>>> 
Answered byhermann.ruckerbauer 8 years 5 months
Hello Ken,during the definition of DDR2 and DDR2 the current return and noisecoupling was considered (as Larry pointed out in the next answer). Asthe CA is referenced to VDD on the DIMM the decoupling would need to beVDD referenced. E. g. in the case of a noise event on VDD this wouldcouple into the CA lines .. so the CA line reference (Vref_CA) shouldsee the same noise in order to compensate such an event.Your assumption to have the VTT as source AND sink would be an argumentfor a decoupling to both, VDD and VSS ... but this is just the DCcurrent path, I'm not sure if this is really a point for the ACcurrent/noise ...HermannOur next Events:================"Open the Black Box of Memory"Seminar on 09/10. October 2012Check our website or contact us for detailsEKH - EyeKnowHowHermann Ruckerbauerwww.EyeKnowHow.deHermann.Ruckerbauer@xxxxxxxxxxxxxVeilchenstrasse 194554 MoosTel.:   +49 (0)9938 / 902 083Mobile: +49 (0)176  / 787 787 77Fax:    +49 (0)3212 / 121 9008schrieb Ken Patterson:> I think the reason to decouple to both VSS and to VDD stems from the VTT> supply being able to source and sink current. Am I correct in my thoughts?>> Ken>> -----
Answered byhermann.ruckerbauer 8 years 5 months
Hello,yes, Vinu's explanation is very good!Just one comment: VTT is just between VDD and GND, so this would be noreason to decouple to VDD. The real issue is the referencing on the DIMM(which comes from the limited number of supply pins on the DIMM connector)Nevertheless I prefer to do a decoupling to both VDD and VSS.This is also some kind of philosophy. Some people think that VSS is astable potential, while VDD is something unstable .. I think both shouldbe handled with the same care. But this means, that both might havenoise (seen in reference to some imaginary solid and fixed potential).Based on this "philosophy" i prefer to have e. g. two same sizecapacitors to VDD and GND compared to two different sized capacitors toGND (or VDD for CA).But thats just my way of looking into any "stable" potential ...HermannOur next Events:================"Open the Black Box of Memory"Seminar on 09/10. October 2012Check our website or contact us for detailsEKH - EyeKnowHowHermann Ruckerbauerwww.EyeKnowHow.deHermann.Ruckerbauer@xxxxxxxxxxxxxVeilchenstrasse 194554 MoosTel.:   +49 (0)9938 / 902 083Mobile: +49 (0)176  / 787 787 77Fax:    +49 (0)3212 / 121 9008schrieb Vinu Arumugham:> My understanding is that on the DIMM, DQ routing is referenced to a VSS > plane and CA routing is referenced to a VDD plane. Therefore VrefCA is > bypassed to VDD and VrefDQ is bypassed to VSS. Since VTT is used to > terminate CA, it is also bypassed to VDD.>> Thanks,> Vinu>> On 06/07/2012 11:29 PM, Tesla wrote:>> Hi, experts>> I read the standard "DDR3 SDRAM Unbuffered DIMM Design Specification">> On the page 32, it states three kinds of decoupling for >> VTT,Vref_DQ,Vref_CApower rail:>> 1 VTT, Minimum of one decoupling capacitor to VDD per every two termination>> resistors>> 2 Vref_CA,Minimum of one decoupling capacitor to VDD per DRAM>> 3 Vref_DQ,Minimum of one decoupling capacitor to VSS per DRAM.>>>> Confusion:>> Why VTT decoupling capacitor to VDD not VSS(usually GND)? will this increase >> noise coupling between VTT and VDD?>> Vref_CA and Vref_DQ has same function as the reference voltage for SSTL-15.>> Vref_CA decoupling capacitor connected to VDD, but the Vref_DQ connected to >> VSS.>>>> I think decoupling capacitors of all above power rails should be connected >> to VSS and corresponding power rail net, this will be better decoupled.>>>>   Thanks.>>>> Tesla>> 
Answered bylarrys 8 years 5 months
The main reason to decouple VTT is to provide a path for trace return current.  If the traces have their return current on Vss, then it important to decouple to Vss.  If traces have their return current on Vdd, then decouple to Vdd.  And if return current is on a combination of both Vdd and Vss, decouple VTT to both of them.  Regards,Larry Smith-----
Answered byemcesd 8 years 5 months 1 day
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Answered byvinu 8 years 5 months 1 day
Yes, but symmetric noise on VDD/VSS w.r.t some external reference means VDD noise w.r.t VSS is 0. We never see that on practical systems!Thanks,VinuOn 06/08/2012 01:30 PM, Hermann Ruckerbauer wrote:> If you have a symmetric noise on VDD and VSS and a decoupling to both> then VTT will see the same noise and everything is fine, right ?>> Hermann>>> Our next Events:> ================>> "Open the Black Box of Memory"> Seminar on 09/10. October 2012>> Check our website or contact us for details>> EKH - EyeKnowHow> Hermann Ruckerbauer> www.EyeKnowHow.de> Hermann.Ruckerbauer@xxxxxxxxxxxxx> Veilchenstrasse 1> 94554 Moos> Tel.: +49 (0)9938 / 902 083> Mobile:       +49 (0)176  / 787 787 77> Fax:  +49 (0)3212 / 121 9008>>> schrieb Vinu Arumugham:>> Hermann,>>>> Regardless of whether VSS/VDD have any noise with respect to some>> external reference, we can be sure that VDD will have noise w.r.t VSS>> ( or if you prefer, VSS will have noise w.r.t VDD).>> Decoupling to both rails will therefore inject noise into VTT even>> when VDD and VSS are perfectly symmetric.>>>> Thanks,>> Vinu>>>> On 06/08/2012 11:55 AM, Hermann Ruckerbauer wrote:>>> Hello Vinu,>>>>>> not exactly, only as long as you think about VSS as fixed potential. As>>> I mentioned I think both are equal designed ... so you can get noise on>>> both VDD or VSS. And both will be transferred equally to VTT ...>>>>>> But as I mentioned .. I think this is more a question of design>>> philosophy ...>>>>>> Hermann>>>>>> Our next Events:>>> ================>>>>>> "Open the Black Box of Memory">>> Seminar on 09/10. October 2012>>>>>> Check our website or contact us for details>>>>>> EKH - EyeKnowHow>>> Hermann Ruckerbauer>>> www.EyeKnowHow.de>>> Hermann.Ruckerbauer@xxxxxxxxxxxxx>>> Veilchenstrasse 1>>> 94554 Moos>>> Tel.:    +49 (0)9938 / 902 083>>> Mobile:    +49 (0)176  / 787 787 77>>> Fax:    +49 (0)3212 / 121 9008>>>>>>>>> schrieb Vinu Arumugham:>>>> Hermann,>>>>>>>>>>>> "Nevertheless I prefer to do a decoupling to both VDD and VSS.">>>>>>>> If you decouple VTT to both VDD and VSS, you create a AC voltage>>>> divider between VDD/VSS and connect it to VTT. So any noise on VDD>>>> w.r.t VSS will be divided in half and be injected on to VTT.>>>> Decoupling to VSS or VDD alone would avoid this noise injection. Do>>>> you agree?>>>>>>>> Thanks,>>>> Vinu>>>>>>>>>>>>>>>> On 06/08/2012 10:14 AM, Hermann Ruckerbauer wrote:>>>>> Hello,>>>>>>>>>> yes, Vinu's explanation is very good!>>>>> Just one comment: VTT is just between VDD and GND, so this would be no>>>>> reason to decouple to VDD. The real issue is the referencing on the>>>>> DIMM>>>>> (which comes from the limited number of supply pins on the DIMM>>>>> connector)>>>>>>>>>> Nevertheless I prefer to do a decoupling to both VDD and VSS.>>>>> This is also some kind of philosophy. Some people think that VSS is a>>>>> stable potential, while VDD is something unstable .. I think both>>>>> should>>>>> be handled with the same care. But this means, that both might have>>>>> noise (seen in reference to some imaginary solid and fixed potential).>>>>> Based on this "philosophy" i prefer to have e. g. two same size>>>>> capacitors to VDD and GND compared to two different sized>>>>> capacitors to>>>>> GND (or VDD for CA).>>>>>>>>>> But thats just my way of looking into any "stable" potential ...>>>>>>>>>> Hermann>>>>>>>>>> Our next Events:>>>>> ================>>>>>>>>>> "Open the Black Box of Memory">>>>> Seminar on 09/10. October 2012>>>>>>>>>> Check our website or contact us for details>>>>>>>>>> EKH - EyeKnowHow>>>>> Hermann Ruckerbauer>>>>> www.EyeKnowHow.de>>>>> Hermann.Ruckerbauer@xxxxxxxxxxxxx>>>>> Veilchenstrasse 1>>>>> 94554 Moos>>>>> Tel.:    +49 (0)9938 / 902 083>>>>> Mobile:    +49 (0)176  / 787 787 77>>>>> Fax:    +49 (0)3212 / 121 9008>>>>>>>>>>>>>>> schrieb Vinu Arumugham:>>>>>> My understanding is that on the DIMM, DQ routing is referenced to>>>>>> a VSS>>>>>> plane and CA routing is referenced to a VDD plane. Therefore>>>>>> VrefCA is>>>>>> bypassed to VDD and VrefDQ is bypassed to VSS. Since VTT is used to>>>>>> terminate CA, it is also bypassed to VDD.>>>>>>>>>>>> Thanks,>>>>>> Vinu>>>>>>>>>>>> On 06/07/2012 11:29 PM, Tesla wrote:>>>>>>> Hi, experts>>>>>>> I read the standard "DDR3 SDRAM Unbuffered DIMM Design>>>>>>> Specification">>>>>>> On the page 32, it states three kinds of decoupling for>>>>>>> VTT,Vref_DQ,Vref_CApower rail:>>>>>>> 1 VTT, Minimum of one decoupling capacitor to VDD per every two>>>>>>> termination>>>>>>> resistors>>>>>>> 2 Vref_CA,Minimum of one decoupling capacitor to VDD per DRAM>>>>>>> 3 Vref_DQ,Minimum of one decoupling capacitor to VSS per DRAM.>>>>>>>>>>>>>> Confusion:>>>>>>> Why VTT decoupling capacitor to VDD not VSS(usually GND)? will>>>>>>> this increase noise coupling between VTT and VDD?>>>>>>> Vref_CA and Vref_DQ has same function as the reference voltage>>>>>>> for SSTL-15.>>>>>>> Vref_CA decoupling capacitor connected to VDD, but the Vref_DQ>>>>>>> connected to VSS.>>>>>>>>>>>>>> I think decoupling capacitors of all above power rails should be>>>>>>> connected to VSS and corresponding power rail net, this will be>>>>>>> better decoupled.>>>>>>>>>>>>>>      Thanks.>>>>>>>>>>>>>> Tesla>>>>>>> 
Answered bybuenos 8 years 5 months 1 day
Hi,I think this has also something to do with reference plances used for the signals.Im my designs I only use GND reference (signals are not adjacent to any VDD polygons), and so decouple the VTT island to GND. My return currents will flow through the RTT resistor into the GND plane then back to the source driver. The driver must have good decoupling between VDD and GND to ensure using only GND plane to be adequate.Standard DIMM and low layer count motherboards often use VDD plane as reference for address bus, but I think its not mandatory, simply providing continuous gnd everywhere on the board pays off: you can route other signals in the same board area referencing everything to gnd only. Good for dense designs.Vref has not much to do with return currents and reference planes, it is to do with setting the center of the AC/DC thresholds at half way between VDD/GND.The Vref pin on the mem/proc should be half way between the VDD and GND. Both VDD and GND have noise on them, and unfortunatelly these noises depend on the time and location too. So, either decouple Vref pins to both VDD/GND to maintain Vref=VDD/2 or decouple to the reference plane(s) used. This is actually not clear to me which choice is better.On the other hand the VTT island will pull the A/C/C signals to its voltage, so if the VTT is decoupled only to GND, then better decoupling the Vref pins in the exact same way. This way the input thresholds will be pulled the same way where the signals are pulled to.Regards,Istvan Nagy-----
Answered byken.patterson 8 years 5 months 1 day
I think the reason to decouple to both VSS and to VDD stems from the VTTsupply being able to source and sink current. Am I correct in my thoughts?Ken-----
Answered byvinu 8 years 5 months 1 day
Hermann,Regardless of whether VSS/VDD have any noise with respect to some external reference, we can be sure that VDD will have noise w.r.t VSS ( or if you prefer, VSS will have noise w.r.t VDD).Decoupling to both rails will therefore inject noise into VTT even when VDD and VSS are perfectly symmetric.Thanks,VinuOn 06/08/2012 11:55 AM, Hermann Ruckerbauer wrote:> Hello Vinu,>> not exactly, only as long as you think about VSS as fixed potential. As> I mentioned I think both are equal designed ... so you can get noise on> both VDD or VSS. And both will be transferred equally to VTT ...>> But as I mentioned .. I think this is more a question of design> philosophy ...>> Hermann>> Our next Events:> ================>> "Open the Black Box of Memory"> Seminar on 09/10. October 2012>> Check our website or contact us for details>> EKH - EyeKnowHow> Hermann Ruckerbauer> www.EyeKnowHow.de> Hermann.Ruckerbauer@xxxxxxxxxxxxx> Veilchenstrasse 1> 94554 Moos> Tel.: +49 (0)9938 / 902 083> Mobile:       +49 (0)176  / 787 787 77> Fax:  +49 (0)3212 / 121 9008>>> schrieb Vinu Arumugham:>> Hermann,>>>>>> "Nevertheless I prefer to do a decoupling to both VDD and VSS.">>>> If you decouple VTT to both VDD and VSS, you create a AC voltage divider >> between VDD/VSS and connect it to VTT. So any noise on VDD w.r.t VSS will be >> divided in half and be injected on to VTT. Decoupling to VSS or VDD alone >> would avoid this noise injection. Do you agree?>>>> Thanks,>> Vinu>>>>>>>> On 06/08/2012 10:14 AM, Hermann Ruckerbauer wrote:>>> Hello,>>>>>> yes, Vinu's explanation is very good!>>> Just one comment: VTT is just between VDD and GND, so this would be no>>> reason to decouple to VDD. The real issue is the referencing on the DIMM>>> (which comes from the limited number of supply pins on the DIMM connector)>>>>>> Nevertheless I prefer to do a decoupling to both VDD and VSS.>>> This is also some kind of philosophy. Some people think that VSS is a>>> stable potential, while VDD is something unstable .. I think both should>>> be handled with the same care. But this means, that both might have>>> noise (seen in reference to some imaginary solid and fixed potential).>>> Based on this "philosophy" i prefer to have e. g. two same size>>> capacitors to VDD and GND compared to two different sized capacitors to>>> GND (or VDD for CA).>>>>>> But thats just my way of looking into any "stable" potential ...>>>>>> Hermann>>>>>> Our next Events:>>> ================>>>>>> "Open the Black Box of Memory">>> Seminar on 09/10. October 2012>>>>>> Check our website or contact us for details>>>>>> EKH - EyeKnowHow>>> Hermann Ruckerbauer>>> www.EyeKnowHow.de>>> Hermann.Ruckerbauer@xxxxxxxxxxxxx>>> Veilchenstrasse 1>>> 94554 Moos>>> Tel.:       +49 (0)9938 / 902 083>>> Mobile:     +49 (0)176  / 787 787 77>>> Fax:        +49 (0)3212 / 121 9008>>>>>>>>> schrieb Vinu Arumugham:>>>> My understanding is that on the DIMM, DQ routing is referenced to a VSS>>>> plane and CA routing is referenced to a VDD plane. Therefore VrefCA is>>>> bypassed to VDD and VrefDQ is bypassed to VSS. Since VTT is used to>>>> terminate CA, it is also bypassed to VDD.>>>>>>>> Thanks,>>>> Vinu>>>>>>>> On 06/07/2012 11:29 PM, Tesla wrote:>>>>> Hi, experts>>>>> I read the standard "DDR3 SDRAM Unbuffered DIMM Design Specification">>>>> On the page 32, it states three kinds of decoupling for >>>>> VTT,Vref_DQ,Vref_CApower rail:>>>>> 1 VTT, Minimum of one decoupling capacitor to VDD per every two >>>>> termination>>>>> resistors>>>>> 2 Vref_CA,Minimum of one decoupling capacitor to VDD per DRAM>>>>> 3 Vref_DQ,Minimum of one decoupling capacitor to VSS per DRAM.>>>>>>>>>> Confusion:>>>>> Why VTT decoupling capacitor to VDD not VSS(usually GND)? will this >>>>> increase noise coupling between VTT and VDD?>>>>> Vref_CA and Vref_DQ has same function as the reference voltage for >>>>> SSTL-15.>>>>> Vref_CA decoupling capacitor connected to VDD, but the Vref_DQ connected >>>>> to VSS.>>>>>>>>>> I think decoupling capacitors of all above power rails should be >>>>> connected to VSS and corresponding power rail net, this will be better >>>>> decoupled.>>>>>>>>>>     Thanks.>>>>>>>>>> Tesla>>>>> 
Answered byvinu 8 years 5 months 1 day
Hermann,"Nevertheless I prefer to do a decoupling to both VDD and VSS."If you decouple VTT to both VDD and VSS, you create a AC voltage divider between VDD/VSS and connect it to VTT. So any noise on VDD w.r.t VSS will be divided in half and be injected on to VTT. Decoupling to VSS or VDD alone would avoid this noise injection. Do you agree?Thanks,VinuOn 06/08/2012 10:14 AM, Hermann Ruckerbauer wrote:> Hello,>> yes, Vinu's explanation is very good!> Just one comment: VTT is just between VDD and GND, so this would be no> reason to decouple to VDD. The real issue is the referencing on the DIMM> (which comes from the limited number of supply pins on the DIMM connector)>> Nevertheless I prefer to do a decoupling to both VDD and VSS.> This is also some kind of philosophy. Some people think that VSS is a> stable potential, while VDD is something unstable .. I think both should> be handled with the same care. But this means, that both might have> noise (seen in reference to some imaginary solid and fixed potential).> Based on this "philosophy" i prefer to have e. g. two same size> capacitors to VDD and GND compared to two different sized capacitors to> GND (or VDD for CA).>> But thats just my way of looking into any "stable" potential ...>> Hermann>> Our next Events:> ================>> "Open the Black Box of Memory"> Seminar on 09/10. October 2012>> Check our website or contact us for details>> EKH - EyeKnowHow> Hermann Ruckerbauer> www.EyeKnowHow.de> Hermann.Ruckerbauer@xxxxxxxxxxxxx> Veilchenstrasse 1> 94554 Moos> Tel.: +49 (0)9938 / 902 083> Mobile:       +49 (0)176  / 787 787 77> Fax:  +49 (0)3212 / 121 9008>>> schrieb Vinu Arumugham:>> My understanding is that on the DIMM, DQ routing is referenced to a VSS>> plane and CA routing is referenced to a VDD plane. Therefore VrefCA is>> bypassed to VDD and VrefDQ is bypassed to VSS. Since VTT is used to>> terminate CA, it is also bypassed to VDD.>>>> Thanks,>> Vinu>>>> On 06/07/2012 11:29 PM, Tesla wrote:>>> Hi, experts>>> I read the standard "DDR3 SDRAM Unbuffered DIMM Design Specification">>> On the page 32, it states three kinds of decoupling for >>> VTT,Vref_DQ,Vref_CApower rail:>>> 1 VTT, Minimum of one decoupling capacitor to VDD per every two termination>>> resistors>>> 2 Vref_CA,Minimum of one decoupling capacitor to VDD per DRAM>>> 3 Vref_DQ,Minimum of one decoupling capacitor to VSS per DRAM.>>>>>> Confusion:>>> Why VTT decoupling capacitor to VDD not VSS(usually GND)? will this >>> increase noise coupling between VTT and VDD?>>> Vref_CA and Vref_DQ has same function as the reference voltage for SSTL-15.>>> Vref_CA decoupling capacitor connected to VDD, but the Vref_DQ connected to >>> VSS.>>>>>> I think decoupling capacitors of all above power rails should be connected >>> to VSS and corresponding power rail net, this will be better decoupled.>>>>>>    Thanks.>>>>>> Tesla>>> 
Answered bygnuarm.2006 8 years 5 months 1 day
Can you explain why using decoupling to both ground and power would be better than just decoupling to ground?  Aren't the power and ground already adequately decoupled across the spectrum?  So if you provide a low impedance to ground aren't you also providing a low impedance to the power rail?RickAt 03:11 AM 6/8/2012, you wrote:>Vtt is nominally 0.5 * Vdd.  In a simple topology where Vtt is derived>with a resistor divider, two caps of equal value one to each rail would>maintain Vtt at 0.5Vdd across frequency.>>Steve>On 6/7/2012 11:29 PM, Tesla wrote:> > Hi, experts> > I read the standard "DDR3 SDRAM Unbuffered DIMM Design Specification"> > On the page 32, it states three kinds of decoupling for > VTT,Vref_DQ,Vref_CApower rail:> > 1 VTT, Minimum of one decoupling capacitor to VDD per every two termination> > resistors> > 2 Vref_CA,Minimum of one decoupling capacitor to VDD per DRAM> > 3 Vref_DQ,Minimum of one decoupling capacitor to VSS per DRAM.> >> > Confusion:> > Why VTT decoupling capacitor to VDD not VSS(usually GND)? will > this increase noise coupling between VTT and VDD?> > Vref_CA and Vref_DQ has same function as the reference voltage for SSTL-15.> > Vref_CA decoupling capacitor connected to VDD, but the Vref_DQ > connected to VSS.> >> > I think decoupling capacitors of all above power rails should be > connected to VSS and corresponding power rail net, this will be > better decoupled.> >> >   Thanks.> >> > Tesla> > 
Answered byvinu 8 years 5 months 1 day
My understanding is that on the DIMM, DQ routing is referenced to a VSS plane and CA routing is referenced to a VDD plane. Therefore VrefCA is bypassed to VDD and VrefDQ is bypassed to VSS. Since VTT is used to terminate CA, it is also bypassed to VDD.Thanks,VinuOn 06/07/2012 11:29 PM, Tesla wrote:> Hi, experts> I read the standard "DDR3 SDRAM Unbuffered DIMM Design Specification"> On the page 32, it states three kinds of decoupling for > VTT,Vref_DQ,Vref_CApower rail:> 1 VTT, Minimum of one decoupling capacitor to VDD per every two termination> resistors> 2 Vref_CA,Minimum of one decoupling capacitor to VDD per DRAM> 3 Vref_DQ,Minimum of one decoupling capacitor to VSS per DRAM.>> Confusion:> Why VTT decoupling capacitor to VDD not VSS(usually GND)? will this increase > noise coupling between VTT and VDD?> Vref_CA and Vref_DQ has same function as the reference voltage for SSTL-15.> Vref_CA decoupling capacitor connected to VDD, but the Vref_DQ connected to > VSS.>> I think decoupling capacitors of all above power rails should be connected to > VSS and corresponding power rail net, this will be better decoupled.>>   Thanks.>> Tesla> 
Answered byweirsi 8 years 5 months 1 day
Vtt is nominally 0.5 * Vdd.  In a simple topology where Vtt is derived with a resistor divider, two caps of equal value one to each rail would maintain Vtt at 0.5Vdd across frequency.SteveOn 6/7/2012 11:29 PM, Tesla wrote:> Hi, experts> I read the standard "DDR3 SDRAM Unbuffered DIMM Design Specification"> On the page 32, it states three kinds of decoupling for > VTT,Vref_DQ,Vref_CApower rail:> 1 VTT, Minimum of one decoupling capacitor to VDD per every two termination> resistors> 2 Vref_CA,Minimum of one decoupling capacitor to VDD per DRAM> 3 Vref_DQ,Minimum of one decoupling capacitor to VSS per DRAM.>> Confusion:> Why VTT decoupling capacitor to VDD not VSS(usually GND)? will this increase > noise coupling between VTT and VDD?> Vref_CA and Vref_DQ has same function as the reference voltage for SSTL-15.> Vref_CA decoupling capacitor connected to VDD, but the Vref_DQ connected to > VSS.>> I think decoupling capacitors of all above power rails should be connected to > VSS and corresponding power rail net, this will be better decoupled.>>   Thanks.>> Tesla>