Double data rate synchronous dynamic random-access memory (DDR SDRAM) is a class of memory integrated circuits used in computers. http://en.wikipedia.org/wiki/DDR_SDRAM

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Power Supply Noise injected Jitter impact on SERD......


Hi All,In my design I have high speed interfaces like DDR4 and PCIe 3.0 interfaceoperating at their ......

asked by rameshp3note lastest answer by carsona

4 years 10 months 6 days

0

votes

1

answers
2499 views

Job Opening at Qualcomm: Signal Integrity Enginee......


Hello,Qualcomm Package Electrical Group has a Job opening in San Diego, CA for a qualified Candidate......

asked by moshiulh

4 years 10 months 6 days

0

votes

0

answers
2548 views

Re: si-list Digest V16 #24


A few things to recognize, folksFirst, ANYONE can build an averaged model which is state space plane......

asked by Steve lastest answer by Steve

4 years 10 months 7 days

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votes

3

answers
3464 views

min trace length


Hi experts,As we know, there are two kinds of applications for DDR, one is SDRAM onboard, and anothe......

asked by chambers.yin lastest answer by chambers.yin

4 years 11 months 12 days

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votes

4

answers
2660 views

High Speed I/O Signal Integrity Engineer with IDT......


Title: Staff Signal Integrity EngineerAs a High Speed I/O Signal Integrity Engineer, you will be res......

asked by Yue.Yu

5 years 10 days

0

votes

0

answers
2303 views

RegardingDual Stripline PCB routing


HiI am planning to design a PCB board using Dual Stipline. The board has several high speed interfac......

asked by VIVEK.VISHWANATH lastest answer by scott

5 years 2 months 11 days

0

votes

3

answers
2367 views

Do SERDES interfaces need Power Aware SI channel ......


*Hi Team,*Could anybody let me know the importance of Power Aware simulation in todayHigh Speed appl......

asked by rameshp3note lastest answer by chris.cheng

5 years 2 months 19 days

0

votes

2

answers
2602 views

DDR3 output timing uncertainty question.


Hi all,How does one estimate the relative output timing uncertainty, between DQ and DQS, for a DDR3 ......

asked by DBanas lastest answer by John.Ellis

5 years 3 months 27 days

0

votes

7

answers
3709 views

Including submodel selection keyword in IBIS mode......


Hi SI users,We have been generating IBIS models for DDR2 memory and have always come across a proble......

asked by Brijesh.Shah lastest answer by Brijesh.Shah

5 years 3 months 18 days

0

votes

3

answers
2561 views

DDR Pre-fetch architecture


Hi,How does DDR Internal Pre-fetch architecture matters with data speed?Regards,Savi

DDR

asked by savi.hwsi lastest answer by hermann.ruckerbauer

5 years 5 months 15 days

0

votes

1

answers
2024 views

Ac threshold timings


Hi ExpertsHere's my question.In ddr3 simulation I have come across AC175, AC150 & AC135.I have confu......

asked by kalyan.krishnan02 lastest answer by kalyan.krishnan02

5 years 7 months 10 days

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votes

5

answers
3884 views

Derating values for DDR3-800/1066/1333/1600 tDS/t......


HI experts:why dose the dq slew rate increase,the tDS and tDH increases at the sametime?Best Regards......

asked by hanmoggq lastest answer by hanmoggq

5 years 7 months 12 days

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votes

6

answers
3266 views
5 years 7 months 17 days

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votes

0

answers
2225 views
5 years 8 months 29 days

0

votes

0

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2832 views

IBIS model for High Impedance State


Samsung Enterprise Portal mySingleP { MARGIN-BOTTOM: 5px; FONT-SIZE: 9pt; FONT-FAMILY: ±¼¸²Ã¼, arial......

asked by sangho9.lee lastest answer by Arpad_Muranyi

5 years 8 months 6 days

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votes

1

answers
2239 views

IBIS 5.0 model for DDR3 component


Hello experts,In the frame of my research work for my Ph. D. thesis in the field of Power Integrity,......

asked by benoit.goral lastest answer by ferhatyaldiz

5 years 8 months 14 days

0

votes

1

answers
3189 views

Tri-state level of DQ signal in DDR3L


Hi,We are capturing DDR3L signals for DVT ( Detailed Validation). Tek Scopecan't able to understand ......

asked by malli.1729 lastest answer by Hermann.Ruckerbauer

5 years 9 months 26 days

0

votes

1

answers
2280 views

DDR4 and PAM4 DesignCon papers


Hi si-listers,I uploaded our DesignCon 2015 technical track papers to:http://signal-integrity.blogs.......

asked by colin_warwick

5 years 9 months 12 days

0

votes

0

answers
2898 views

Signal Integrity Job opening at Xilinx


Xilinx has a Signal Integrity Sr. Staff Engineer opening immediately in the Package Design Departmen......

asked by ray.anderson

5 years 9 months 14 days

0

votes

0

answers
2366 views
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